Draw the output signals $C_1$ and $C_2$ for the given combination of gates as shown in the figure.

(N/A) For the circuit in figure $(3)$:
$Y_1 = \overline{A}$,$Y_2 = \overline{B}$.
The output of the $NAND$ gate is $Y = \overline{Y_1 \cdot Y_2} = \overline{\overline{A} \cdot \overline{B}} = A + B$.
The final $NOT$ gate gives $C_1 = \overline{Y} = \overline{A + B}$.
This is the Boolean expression for a $NOR$ gate.
Based on the input signals $A$ and $B$,the output $C_1$ is high $(1)$ only when both $A$ and $B$ are low $(0)$,which occurs in the interval $t = 4 \text{ s}$ to $t = 5 \text{ s}$.
For the circuit in figure $(4)$:
$Y_1 = \overline{A}$,$Y_2 = \overline{B}$.
The output of the $NOR$ gate is $C_2 = \overline{Y_1 + Y_2} = \overline{\overline{A} + \overline{B}} = \overline{\overline{A \cdot B}} = A \cdot B$.
This is the Boolean expression for an $AND$ gate.
Based on the input signals $A$ and $B$,the output $C_2$ is high $(1)$ only when both $A$ and $B$ are high $(1)$,which occurs in the interval $t = 1 \text{ s}$ to $t = 2 \text{ s}$.