In the circuit given below,V(t) is the sinuso | vedclass

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(D) During the positive half cycle of the input $V(t)$,the diode $D_1$ is forward biased and $D_2$ is reverse biased. The current flows through the lo

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has different peak values during positive and negative half cycles

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(D) During the positive half cycle of the input $V(t)$,the diode $D_1$ is forward biased and $D_2$ is reverse biased. The current flows through the loop containing $R_1$ and $R$. The voltage drop across $R$ is given by the voltage divider rule: $V_{AB} = V(t) \cdot \frac{R}{R + R_1}$.During the negative half cycle of the input $V(t)$,the diode $D_2$ is forward biased and $D_1$ is reverse biased. The current flows through the loop containing $R_2$ and $R$. The voltage drop across $R$ is given by: $V_{AB} = |V(t)| \cdot \frac{R}{R + R_2}$.Since $R_1 = 100 \ \Omega$ and $R_2 = 150 \ \Omega$,the voltage division factors $\frac{R}{R + 100}$ and $\frac{R}{R + 150}$ are different.Therefore,the peak values of the output voltage $V_{AB}$ during the positive and negative half cycles are different.

In the circuit given below,$V(t)$ is the sinusoidal voltage source. The voltage drop $V_{AB}(t)$ across the resistance $R$ is:

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