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(B) The circuit consists of a $NAND$ gate, a $NOR$ gate, and a $NOR$ gate at the output stage.$1$. The inputs to the $NAND$ gate are $1$ and $0$. The

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$1, 0, 0$

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(B) The circuit consists of a $NAND$ gate, a $NOR$ gate, and a $NOR$ gate at the output stage.$1$. The inputs to the $NAND$ gate are $1$ and $0$. The output of a $NAND$ gate is $Y_1 = \overline{1 \cdot 0} = \overline{0} = 1$.$2$. The inputs to the $NOR$ gate are $1$ and $0$. The output of a $NOR$ gate is $Y_2 = \overline{1 + 0} = \overline{1} = 0$.$3$. The inputs to the final $NOR$ gate are $Y_1 = 1$ and $Y_2 = 0$. The output is $Y_3 = \overline{Y_1 + Y_2} = \overline{1 + 0} = \overline{1} = 0$.Thus, the values are $Y_1 = 1, Y_2 = 0, Y_3 = 0$.

In the following logic circuit, the values of $Y_1, Y_2$ and $Y_3$ are respectively

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