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(D) Let us analyze the circuit step by step:$1$. The top $NAND$ gate has inputs $1$ and $0$. The output is $(1 \cdot 0)' = 0' = 1$.$2$. The middle $AN

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$(0,0,0)$

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(D) Let us analyze the circuit step by step:$1$. The top $NAND$ gate has inputs $1$ and $0$. The output is $(1 \cdot 0)' = 0' = 1$.$2$. The middle $AND$ gate has inputs $1$ and $1$. The output is $1 \cdot 1 = 1$.$3$. The bottom $OR$ gate has inputs $0$ and $1$. The output is $0 + 1 = 1$.$4$. The top $NOR$ gate receives inputs from the $NAND$ gate $(1)$ and the $AND$ gate $(1)$. Its output $y_1 = (1 + 1)' = 1' = 0$.$5$. The bottom $NOR$ gate receives inputs from the $AND$ gate $(1)$ and the $OR$ gate $(1)$. Its output $y_2 = (1 + 1)' = 1' = 0$.$6$. The final $AND$ gate receives inputs $y_1 = 0$ and $y_2 = 0$. Its output $y_3 = 0 \cdot 0 = 0$.Therefore, the values are $y_1 = 0, y_2 = 0, y_3 = 0$.

Six logic gates are connected as shown in the figure. The values of $y_1, y_2$ and $y_3$ respectively are

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