The following figure shows an AND logic gate | vedclass

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(A) For an $AND$ gate,the output $C$ is high $(1)$ only when both inputs $A$ and $B$ are high $(1)$.If either input is low $(0)$,the output $C$ is low

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(A) For an $AND$ gate,the output $C$ is high $(1)$ only when both inputs $A$ and $B$ are high $(1)$.If either input is low $(0)$,the output $C$ is low $(0)$.Looking at the provided waveforms:- $A$ is high during the second and fourth time intervals.- $B$ is high during the second and third time intervals.- The output $C = A \cdot B$ will be high $(1)$ only during the second time interval where both $A$ and $B$ are high.- Therefore,the waveform for $C$ will show a high pulse only during the second interval.

The following figure shows an $AND$ logic gate circuit with two inputs $A$ and $B$ and the output $C$. The voltage waveforms of $C$ will be:

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