The output Y for the inputs A and B of the ci | vedclass

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(D) The given circuit consists of four $NAND$ gates. Let the inputs be $A$ and $B$.
$1$. The first $NAND$ gate (top) has inputs $A$ and the output of

Vedclass · Accepted Answer

$A$
			$B$
			$Y$
		
		
			$0$
			$0$
			$0$
		
		
			$0$
			$1$
			$1$
		
		
			$1$
			$0$
			$1$
		
		
			$1$
			$1$
			$0$

Vedclass · Answer

(D) The given circuit consists of four $NAND$ gates. Let the inputs be $A$ and $B$.
$1$. The first $NAND$ gate (top) has inputs $A$ and the output of the middle $NAND$ gate (which acts as a $NOT$ gate for $A$ and $B$ combined, but here it is a $NAND$ gate with inputs $A$ and $B$). Let the middle gate output be $C = \overline{A \cdot B}$.
$2$. The top $NAND$ gate has inputs $A$ and $C$. Its output is $Y_1 = \overline{A \cdot C} = \overline{A \cdot (\overline{A \cdot B})} = \overline{A \cdot (\overline{A} + \overline{B})} = \overline{A \cdot \overline{A} + A \cdot \overline{B}} = \overline{0 + A \cdot \overline{B}} = \overline{A \cdot \overline{B}} = \overline{A} + B$.
$3$. Similarly, the bottom $NAND$ gate has inputs $B$ and $C$. Its output is $Y_2 = \overline{B \cdot C} = \overline{B \cdot (\overline{A \cdot B})} = \overline{B \cdot (\overline{A} + \overline{B})} = \overline{B \cdot \overline{A} + B \cdot \overline{B}} = \overline{B \cdot \overline{A} + 0} = \overline{B \cdot \overline{A}} = \overline{B} + A$.
$4$. The final $NAND$ gate has inputs $Y_1$ and $Y_2$. Its output is $Y = \overline{Y_1 \cdot Y_2} = \overline{(\overline{A} + B) \cdot (\overline{B} + A)} = \overline{\overline{A} \cdot \overline{B} + \overline{A} \cdot A + B \cdot \overline{B} + B \cdot A} = \overline{\overline{A} \cdot \overline{B} + 0 + 0 + A \cdot B} = \overline{\overline{A} \cdot \overline{B}} \cdot \overline{A \cdot B} = (A + B) \cdot (\overline{A} + \overline{B}) = A \cdot \overline{A} + A \cdot \overline{B} + B \cdot \overline{A} + B \cdot \overline{B} = 0 + A \cdot \overline{B} + \overline{A} \cdot B + 0 = A \oplus B$.
Thus, the circuit represents an $XOR$ gate. The truth table for $XOR$ is given in option $D$.

The output $Y$ for the inputs $A$ and $B$ of the circuit is given by the truth table of the shown circuit:

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