When three NAND logic gates are connected as | vedclass

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(C) Let the inputs be $A$ and $B$.Each of the first two $NAND$ gates has its inputs shorted,which makes them act as $NOT$ gates.Therefore,the output o

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$OR$

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(C) Let the inputs be $A$ and $B$.Each of the first two $NAND$ gates has its inputs shorted,which makes them act as $NOT$ gates.Therefore,the output of the first $NAND$ gate is $\overline{A}$ and the output of the second $NAND$ gate is $\overline{B}$.These outputs $\overline{A}$ and $\overline{B}$ are fed as inputs to the third $NAND$ gate.The output $Y$ of the third $NAND$ gate is given by $Y = \overline{(\overline{A} \cdot \overline{B})}$.Using De Morgan's theorem,$\overline{X \cdot Y} = \overline{X} + \overline{Y}$.So,$Y = \overline{(\overline{A})} + \overline{(\overline{B})} = A + B$.Since the output $Y = A + B$ represents an $OR$ gate,the equivalent logic gate is $OR$.

$A$	$B$	$Y$
$0$	$0$	$1$
$0$	$1$	$0$
$1$	$0$	$1$
$1$	$1$	$1$

When three $NAND$ logic gates are connected as shown in the figure,then the logic gate equivalent to the circuit is

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