Consider two npn transistors as shown in the | vedclass

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(A) The circuit consists of two $npn$ transistors connected in series between the output node $C$ and the ground.For the output $C$ to be low $(0 \, V

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$A \, NAND \, B$

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(A) The circuit consists of two $npn$ transistors connected in series between the output node $C$ and the ground.For the output $C$ to be low $(0 \, V)$,both transistors must be in the '$ON$' state (conducting),which happens when both inputs $A$ and $B$ are high $(5 \, V)$.If either $A$ or $B$ is low $(0 \, V)$,the corresponding transistor is '$OFF$',and the output $C$ is pulled up to $5 \, V$ (high) through the resistor.This behavior follows the truth table of a $NAND$ gate:- If $A=0, B=0$,then $C=1$- If $A=0, B=1$,then $C=1$- If $A=1, B=0$,then $C=1$- If $A=1, B=1$,then $C=0$Thus,the output at $C$ corresponds to $A \, NAND \, B$ or $\overline{A \cdot B} = C$.

Consider two $npn$ transistors as shown in the figure. If $0 \, V$ corresponds to false and $5 \, V$ corresponds to true,then the output at $C$ corresponds to:

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